Constraint Sensitive Applications: Reducing Amplifier Power Consumption of SAR ADC Driver

Figure 1 below directly shows the power consumption of our 12 bit, 4mspsads7881sar ADC, which is a good example of the significant reduction in power consumption.

Figure 1: comparison of ads7881 power consumption and sampling rate

When operating at high clock rate, the only way to save power is to reduce the supply voltage. But this is not always feasible. When using SAR ADC to monitor applications, low duty cycle should be considered if few events will increase the sampling speed when the system is fully awake.

This is good for ADC, but it does not answer the question of how to significantly reduce the power consumption of operational amplifier. So what should we do?

Ads7881 is a 12 bit ADC with a voltage input range of 0V to 2.5V.

I chose opa836 as the amplifier because it can use the same power supply as ads7881. Using 5V power supply, we can minimize the power consumption of ADC and its driver while maintaining the voltage within the input dynamic range.

Opa836 is a 1mA operational amplifier with excellent swing function and linearity in 2x2mm QFN package. It is an ideal choice for battery powered applications. Although it is a rail to rail output (RRO) device, its output can swing to ground only when a small amount of negative power is generated. Positive output has the same limitation, but it doesn't make sense here. It should be noted that the product manual of opa836 clearly distinguishes the minimum / maximum linear output voltage from the saturated output voltage.

For high and low voltage rails, the reserved voltage space for linear operation is 150 / 250Mv, while the reserved voltage space for saturated operation is 15 / 43mv. In addition, since the input of opa836 is not rail to rail input (RRI) and only includes grounding, the voltage range may only be limited to - 0.2V to 3.9v. A reasonable way to avoid this limitation is to use opa836 with a gain of more than 1V / v. Since the maximum input voltage range of ads7881 is limited by the 2.5V reference voltage, and the only limitation we face is the negative rail at the output, there is no problem with the unit gain operation. Because opa836 is a high-speed amplifier, we will obtain a bandwidth of more than 56mhz and a slew rate of more than 100V / MS to ensure that the bandwidth remains constant with any signal level.

The least significant bit (LSB) of ads7881 is about 610mv. The maximum input offset voltage of opa836 is 500uv, which can fully meet the needs of 12 bit applications.

Since the clock rate of the ADC can be controlled, a signal can be generated in the microcontroller to enable / disable opa836 with appropriate timing. The PD pin of opa836 can be easily synchronized with the busy pin, convst pin or nap pin of ads7881 to put opa836 in disabled mode. The main problems to be solved now are the on time of the amplifier and the forced deceleration time constant of the filter interface between the operational amplifier and ADC.

As shown in Figure 2 below, opa836 has shutdown function. Its opening / closing speed is quite fast and can easily adapt to high duty cycle.

Figure 2: opa836 enable / disable response

The biggest remaining problem is the filter time constant after the amplifier.

The way to solve this problem is to control the output voltage of the amplifier output when the amplifier is in off mode, as shown in Figure 3.

Figure 3: maintaining the common mode voltage output of the amplifier in disabled mode

Figure 4: opa836 enable / disable response at medium voltage maintained at the output

It can be seen that the only difference between Fig. 2 and Fig. 4 is that the common mode is different, and the amplifier still has the same on / off time constant. When the ADC enters the hold state from the sampling state, the only function of the amplifier is to maintain an appropriate common mode voltage to help arrange the ADC for the next conversion. When the operational amplifier is in disabled mode, this can be replaced by a resistive voltage divider to save power.

Constraint Sensitive Applications: Reducing Amplifier Power Consumption of SAR ADC Driver 1

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