Forward Converter of Active Clamp Topology Turn Off Reset Switch

Active clamp topology is one of many popular topologies because it allows efficient conversion of bus voltage into required voltage on Logic IC in an electronic subsystem. An article reviewing the active clamp topology turn off reset switch has been published [1]. This article completely introduces the switching cycle. In addition, the paper also describes the conversion of the main switch from "on" to "off", as well as the voltage and current of the opening point circuit of the "active clamp" switch. This description of the active clamp switch is mainly aimed at the continuous current in the output inductance of the active clamp forward converter. The transformer mentioned in this paper is a theoretical model, which describes independent components such as drain inductance ll, magnetization inductance LM and coupling windings NP and ns. The introduction starts with the midpoint of the power distribution of the cycle, and takes the circuit shown in Fig. 1 as the basis for discussion. Arrows indicate positive current. Due to its inherent body diode and drain source capacitance, switches Q1 (active clamp switch) and Q2 are also shown in the figure. We can also see Q3 and Q4 gate drain capacitors because they affect the current.

Figure 3 voltage on transformer pin 2 and pin 3. The voltage increase on pin 2 (i.e. the voltage at time T1) is reflected in the whole transformer winding. This causes the voltage on pin 4 to drop. Since the voltage of NP and NS windings must be balanced, there are voltage changes in the drain source capacitance of Q4 and the gate leakage capacitance of Q3 and Q4. The current in lout will not change greatly, so the current flowing out of these three capacitors must be the result of the change of is and IP. The small change of current in IP leads to the change of primary and secondary capacitor voltage at a stable rate. At this time, when Q3 is about to turn off, the output inductor can pull down all its required current through the FET itself (the gate resistance delays the FET turning off). The main diode of Q4 is reverse biased. During this part of the conversion, the voltage of pin 2 is still lower than VIN, so there is no reason for the main current, i.e. iin flowing into the transformer, to drop. The voltage at both ends of the output inductor changes with the voltage drop of pin 4 to reflect the gradual drop of the main winding voltage. Since the voltage of transformer pin 4 decreases continuously, the voltage at both ends of the output inductor will change. Now, the output voltage Vout exceeds the voltage of transformer pin 4. These factors change at a fixed rate because iin continuously linearly charges the drain source capacitors of Q1 and Q2 until the occurrence time T2, that is, when the voltage of pin 2 reaches VIN (50V), the drain voltage of Q1 reaches – 50V, and the voltage of pin 4 reaches zero v. During time T2 to T3, the current flowing through the primary side drain inductance is still almost the same as at the beginning of conversion, and the voltage of pin 4 decreases continuously. This is reflected in the voltage of pin 2, which exceeds the voltage of transformer pin 1. Any change in the input current is caused by the charging and discharging of the output switch gate source capacitance, and this change is very small. Reversing the primary side voltage can continue to reduce the voltage of pin 4 below the ground level, while pin 3 remains at the ground level because Q3 is continuously closed, see Figure 3. The voltage drop at both ends of FET Q4 is not enough to pass current through the main diode of Q4. Meanwhile, Q3 has not been completely closed. This forces the output inductor to continuously absorb power from the secondary side of the transformer. As a result, a continuous current appears on the primary side and the voltage rises on pin 2. This situation will continue until time T3, and the main diode of its Q4 begins to conduct electricity. Now, the output inductance current can be absorbed from transformer pin 4 and flow through Q4. The primary drain inductance will now form a voltage to balance the rising voltage on pin 2 so that the current can be continuously absorbed. This situation begins to decrease, which can reflect the reduced input current iin flowing through Q3, because IOUT current begins to convert to Q4 main diode. Time T3 to T4 reflects the conversion from the current drawn from the NS winding to the output current IOUT flowing through the Q4 main diode. The decrease of NP and NS winding current is represented by the voltage slope of transformer pin 2, which slows down and flattens with the decrease of NP current flowing through the primary side of the transformer. At the same time, the voltage on pin 3 continues to rise, which is a negative voltage as in the case of pin 4. The result is a small change in the approximate zero of transformer pin 3 and pin 4, but it produces a positive voltage drift of the whole winding. This will turn off Q3 and turn on Q4. The current necessary to obtain this result charges the gate drain capacitor of Q4, discharges the gate drain capacitor of Q3, enters pin 4, and finally flows out of pin 3. This current is provided by the primary side magnetization current, which is located at the peak at this point in the cycle. The magnetizing current im flowing through NP flows in the reverse direction of IP. This reverses the is current so that the gate of Q4 is charged. Since the magnetization current im will now flow efficiently through NP, it now absorbs current from VIN and causes it to charge the drain source capacitors of Q1 and Q2. Therefore, the current from pin 2 to transformer pin 2 voltage is very little (or no). As a result, a relatively stable voltage appears on pin 2 between T3 and T4. At this time, the cycle is almost over. Q4 is conductive through the internal diode and will be turned on, but it will be difficult to turn on from T4 to T5. For the time period between T4 and T5, the magnetizing current is shunted between charging the drain source capacitance of Q1 and Q2 and discharging the gate drain capacitance of Q3, and further charging the Q4 gate drain capacitance. Since these capacitors are nonlinear and the voltage at both ends of Q3 keeps rising, the amount of current required will not be a constant. The current im comes from LM, so the voltage on pin 2 will reflect the nonlinearity of the conversion. At T5, the drain source voltage of Q1 climbs from – 2 VIN to the diode voltage drop above the ground level, and the internal body diode begins to conduct electricity. That is, any current flowing out of pin 2 again will now change the voltage of Cr, which is a larger capacitance. Therefore, this change will be extremely slow and negligible compared with what has already occurred. At this time, transistor Q1 can be turned on in a lossless manner. This completes the lossless primary side switching operation. The secondary side conversion is also relatively lossless because the current switching from one rectifier to another is completed at zero voltage through the internal parasitic body diode.

conclusion

In conclusion, a full understanding of the conversion sequence in this part of the cycle can lead to a better design. We have understood the role of each element in the transformer and output switch when the main switch is closed from changing the output switch to opening the clamp switch.

Forward Converter of Active Clamp Topology Turn Off Reset Switch 1

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